`include "timescale.v"

module onu_phy (
	input 		   Gtx_clk					,//used only in GMII mode
	input 		   Tx_en					,
	input 		   Tx_er					,
	input  [7:0]   Txd						,

	output reg 	   Rx_clk					,
	output reg 	   Rx_dv					,
	output reg	   Rx_er					,
	output reg [7:0] Rxd						,

	output reg	   Col						,	
	output reg	   Crs						

	// output 		   Tx_clk					,//used only in MII mode
	// input  [2:0]   Speed				
	);

initial begin
  Rx_clk = 0;
  forever #4 Rx_clk = ~Rx_clk;			//125M
end

//write data by PLI (Rx for MAC)
initial begin
  Rx_dv = 0;
  Rxd = 8'hxx;
  Rx_er = 0;
  Col = 0;				//no useful
  Crs = 0;
end

always@(posedge Rx_clk)
begin
  // send eth frame by PLI
  #1 $trans_eth_frame(Rx_dv, Rx_er, Rxd);
end




//read data by PLI (Tx for MAC)
reg 			  recv_flag;
initial recv_flag = 1'b0;

always@(posedge Gtx_clk)
begin
  if(Tx_en)
  begin
	recv_flag <= 1'b1;
	$recv_eth_frame(Tx_er, Txd);		//receive data which the MAC transmit
  end
  else			//Tx_en de-asserted
  begin
	if(recv_flag) begin
	  recv_flag <= 1'b0;
	  $recv_eth_frame_finish;
	end
  end
end

//////////////////////////////////////////////////////////////////////
// this file used to simulate Phy.
// generate clk and loop the Tx data to Rx data
// full duplex mode can be verified on loop mode.
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// internal signals
//////////////////////////////////////////////////////////////////////
// reg				Clk_25m			;//used for 100 Mbps mode
// reg				Clk_2_5m		;//used for 10 Mbps mode
//wire			Rx_clk			;
//wire			Tx_clk			;//used only in MII mode
//////////////////////////////////////////////////////////////////////
// always 
// 	begin
// 	#20		Clk_25m=0;
// 	#20		Clk_25m=1;
// 	end
	
// always  
// 	begin
// 	#200	Clk_2_5m=0;
// 	#200	Clk_2_5m=1;
// 	end   



// assign 			  Rx_clk	  = Gtx_clk;

// assign 	Rx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;        
// assign 	Tx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
	
// assign	Rx_dv	=Tx_en	;
// assign	Rxd		=Txd	;
// assign	Rx_er	=0		;
// assign	Crs    	=Tx_en	;
// assign  Col		=0		;

endmodule